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Calypto Design Systems

The Catapult® and PowerPro® family of products enables ASIC, SOC and FPGA designers to quickly create fully-verified, power-optimized RTL for downstream synthesis and physical design.

2933 Bunker Hill Lane, Suite 210, Santa Clara, CA 95054, United States

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Using the Catapult High-Level Synthesis Platform, designers have the option of using C, SystemC or C++ as a design entry language to dramatically shorten the design and verification cycle by producing correct-by-construction, error-free, power-optimized RTL.

The PowerPro RTL Low-Power Platform enables designers to analyze both static and dynamic RTL power usage and either automatically or manually create power-optimized RTL that includes memory and leakage power optimization. The SLEC® formal verification products work with both platforms to formally verify the RTL without the need for time-consuming simulation and complex testbenches. All products are tightly integrated, to enable dramatic reduction in time to market and power usage.

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11 - 30

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  • Location:

    Other: 2933 Bunker Hill Lane, Suite 210, Santa Clara, CA 95054, United States